A recent direction for computer architecture is towards the simplification of instruction execution. An example of such an architecture is the Reduced Instruction Set Computer (RISC) architectures that have been designed to increase the speed of instruction execution. A goal of RISC architecture is to provide computer instructions that can be executed in a single clock cycle. Therefore, by executing more instructions per unit of time, the efficiency of the computer system is increased.
One subset of instructions that are executed by computers are mask instructions. A mask instruction is commonly performed by a logical AND operation between two data words. One data word, the mask word, includes 1's in bit positions where the bit values of the word to be operated on are to remain unchanged. The mask word contains 0's in those bit locations that are to be masked out of the word to be operated on. In some traditional systems, the mask operation will take several cycles.
Another operation related to the mask operation is merge operation. In the merge operation a portion of data in a first data word is inserted into bit locations in a second data word. The locations of the insertion are defined by a bit mask. The merge operation also takes several clock cycles since the initial asking operation and the insertion operation usually occur at different times.
A merge unit performs the mask and insert under mask operations previously described. Also, it is common for the merge unit to be used with a rotator to perform shift operations, i.e., where the bit values of a word are rotated relative to their initial bit locations and the bits which "wrap around" are suppressed. In a traditional central processing unit (CPU), an arithmetic logic (ALU) is provided in parallel with the merge unit. The ALU performs arithmetic operations on data words provided to it. These arithmetic operations include Boolean logic operations.
U.S. Pat. No. 4,569,016 entitled "Mechanism for Implementing One Machine Cycle Executable Mask and Rotate Instructions in a Primitive Instruction Set Computer System" discloses a mechanism for performing a single cycle mask and rotate instruction.
U.S. Pat. No. 3,982,229 entitled "Combinational Logic Arrangement" discloses a circuit for performing shift rotate and insert under mask operations.
U.S. Pat. No. 4,139,899 entitled "Shift Network Having a Mask Generator and a Rotator" discloses a circuit for performing rotation, shift and mask vector generation functions.
U.S. Pat. No. 4,085,447 entitled "Right Justified Mask Transfer Apparatus" discloses a circuit for performing a logical bit by bit ANDing of a multibit data word with a multibit mask such that only those bit positions of the data word for which the corresponding bits of the mask word are of a predetermined binary value are collected contiguously in a mask transfer . register and wherein all other bit positions are ignored.
U.S. Pat. No. 4,012,722 entitled "High Speed Modular Mask Generator" discloses a circuit for generating mask words.
IBM Technical Disclosure Bulletin, Vol. 27, No. 11, Apr., 1985, pages 6419-6421, entitled "Processor Unit Mask Generation Control" discloses an arithmetic logic unit containing a mask generator to build a 32 bit mask string. The masks provided are used to perform shift and rotate instructions. IBM Technical Disclosure Bulletin, Vol. 27, No. 1B, June 1984, pages 747-750, entitled "ALU Merge Operation" discloses a merge circuit within a arithmetic logic unit.
The above prior art addresses the merge, mask and Boolean logic operations. However, the prior art does not disclose the capability to perform both Boolean logic operations and merge or mask operations within the same circuit. It is an object of the present invention to provide a capability to perform either merge, mask or Boolean logic operations within a single circuit. It is also an object of the present invention to perform such operations within a single clock cycle.